Technological advances in semiconductor integrated circuit (IC) materials, design, processing, and manufacturing have enabled ever-shrinking IC devices, where each generation has smaller and more complex circuits than the previous generation.
As semiconductor circuits composed of devices such as metal-oxide-semiconductor field effect transistors (MOSFETs) are adapted for high voltage applications, such as high voltage lateral diffusion metal-oxide-semiconductor devices (HV LDMOSs) including a type of HV LDMOS known as high voltage lateral insulated gate bipolar transistors (HV LIGBTs), problems arise with respect to varying threshold voltage. MOS fabrication process flows may include multiple high concentration implantations. Unfortunately, the multiple implantations also reduce gains of parasitic BJT that can latch-up and affect device performance. A parasitic BJT is a part of the LIGBT that allows a high current to flow when the transistor is turned on. When the LIGBT is on, the electrons flow through the channel of the LIGBT and holes flow through the parasitic BJT at the same time. Thus, a low-impedance path is formed in the parasitic BJT to allow a high current for the LIGBT. Unwanted resistance in the parasitic BJT can cause the LIGBT to overheat.
For a normally operating LIGBT, the parasitic BJT turns off when the LIGBT is off. An internal latch-up circuit for the LIGBT refers to the condition when the parasitic BJT continues to flow even when the LIGBT is off. The continued hole current can damage the transistor and cause a product to fail. While various methods including use of a deep p-type well has been developed to reduce parasitic BJT gain and reduce the impedance in the parasitic BJT path, a HV LIGBT devices having a low parasitic BJT gain and an uniform threshold voltage and a method for making the same continue to be sought.
Various embodiments will be explained in detail with reference to the accompanying drawings.